Load: LD r,r' LD r,n LD r,(HL) LD (HL),n LD A,(nn) LD (nn),A LD dd,nn LD (BC/DE),A LD (nn),BC/DE/SP LD BC/DE/SP,(nn)
Stack: PUSH POP LD SP,HL
8-bit arithmetic: ADD ADC SUB SBC AND OR XOR CP INC DEC NEG
16-bit arithmetic: ADD HL,ss ADC/SBC HL,ss INC/DEC ss
Jumps: JP JP cc JR JR cc DJNZ CALL CALL cc RET RET cc RST
Bit ops: RLC RRC RL RR SLA SRA SRL BIT SET RES (CB prefix)
Control: NOP HALT DI EI IM CPL SCF CCF DAA EX DE,HL EXX EX AF,AF'
Block ops: LDI LDD LDIR LDDR CPI CPD CPIR CPDR (ED prefix)
Interrupts: DI/EI, IM 0/1/2, RETN/RETI, real shadow registers, plus a manual "🔔 INT" button and an optional 50Hz auto-interrupt (like the ULA)
I/R registers: LD I,A LD A,I LD R,A LD A,R — IM2 uses I for the vector table lookup
I/O: IN A,(n) OUT (n),A — port 1 is shown as a text console
Index registers: LD IX,nn LD (IX+d),r/n LD r,(IX+d) INC/DEC (IX+d) ADD IX,pp PUSH/POP IX JP (IX) BIT/SET/RES b,(IX+d) — same for IY, including the undocumented IXH/IXL/IYH/IYL half-registers
Directives: ORG EQU DB/DEFB DEFM DW/DEFW DS/DEFS and LABEL:
File: the "Load" and "Download" buttons read/save the code as plain .z80 text
Screen: writing with LD (nn),A to 0x4000–0x57FF (pixels) or 0x5800–0x5AFF (color, same as the ZX Spectrum) draws instantly
Not implemented: I/O block instructions (INI/OUTI/INIR/OTIR…), RRD/RLD, and cycle-accurate timing — LDIR/CPIR run as a single atomic step rather than being interruptible mid-block instruction by instruction.